The present invention lies in the integrated technology field. More specifically, the invention pertains to an integrated circuit which is formed on a chip and which has a plurality of modules, common power supply pins for the modules, and capacitive buffers for buffering the power supply.
Two different prior art power supply concepts for supplying power to an integrated circuit formed on a chip are shown in FIGS. 1, 1A and 2, 2A. FIG. 1 and FIG. 2 show schematic plan views of the IC and of the integrated circuit, while FIG. 1A and FIG. 2 show the respective equivalent circuit diagrams of the circuits according to FIGS. 1 and 2. In these figures, the respective dynamic current flow is shown with arrows. Dynamic current flow is to be understood as meaning that current flow for supplying the modules of the integrated circuit which corresponds to the current power demand or switching current of the modules.
A power supply concept for an integrated circuit of an earlier design which is formed on a chip and which does not have any buffers is shown in FIG. 1 and FIG. 1A. In FIG. 1, the chip is generally designated with the reference numeral 1. An integrated circuit, which comprises, by way of example, four modules 2, 3, 4 and 5 is formed on the chip 1. The power supply of these modules, which can be any desired circuits, is provided, for example, from two supply terminals 6 and 7, referred to as pins 6, 7 which can be arranged at the edge of the chip 1. The supply pins 6, 7 are connected to two supply tracks 8, 9 which are spaced apart laterally and which extend linearly and parallel to one another. The power supply terminals of the modules 2, 3, 4, 5 are each connected to the supply tracks 8, 9 via one pair or a plurality of pairs of connecting tracks. These connecting tracks run perpendicular to the supply tracks 8, 9 and are designated by the reference numerals 10 to 13 in the equivalent circuit diagram FIG. 1A.
In FIG. 1A, for the sake of simplicity, the modules 2, 3 and 4, 5 which are each at the same height with respect to supply tracks 8, 9 are represented as a uniform module A and B. The ohmic character of the supply tracks 8, 9 is represented in FIG. 1A by resistors, namely by the resistors R1, R2 and R3, R4 located on these lines. The connecting tracks (double) to the module A are designated by 10, 11 and the corresponding connecting tracks for the (double) module B are designated by 12, 13. Instead of the connecting pins 6, 9, an external d.c. source, which is designated by the reference numeral 14 and is connected to the connecting pins 6, 7, is shown in the equivalent circuit diagram according to FIG. 1A. The low-impedance configuration of the supply tracks 8, 9 and of the connecting tracks 10, 11 and 12, 13 ensures the essentially unimpeded supply of even high, necessary switching currents from the external power source 14 to the modules via the supply pins 6, 7. However, because, in this power supply concept, no measures are taken to screen the dynamic currents drawn from the modules 1 to 4 during operation from the external system, for example components on a circuit board on which the chip 1 is arranged, there is the risk of the chip 1 outputting relatively high electromagnetic interference radiation (EMD) into this environment.
In order to limit this problem of relatively high interference radiation, in the integrated circuit shown in FIGS. 2 and 2A, an appropriate screening measure is taken in the form of capacitive buffer devices. Apart from these capacitive buffers, the circuit in FIGS. 2, 2A corresponds to the circuit in FIGS. 1, 1A described above, for which reason corresponding parts are provided with the same reference numerals and it is not necessary to further describe them. The capacitive buffers are in the form of two capacitors 15, 16 which are implemented as on-chip capacitors and are connected in parallel with the supply tracks 8, 9, specifically using connecting tracks which run parallel to the connecting tracks for the modules 2, 3, 4 and 5. The two capacitive buffers and capacitors 15, 16 are arranged between the pairs of modules 2, 3 and 4, 5 and are represented in the equivalent circuit diagram according to FIG. 2A by a single capacitor C which is arranged between the pairs of modules A, B downstream of the (double) module A and upstream of the (double) module B. Owing to this assignment of the capacitor C, the resistors R2, R4 in the supply lines 8, 9 in FIG. 1A are represented in a split form as resistors R2A, R2b and R4a, R4b. 
In the design of that chip power supply it was assumed that the capacitive buffers prevent interference currents owing to high switching currents for the modules being extracted into the external system. However, it has become apparent that that interference suppression measure applies essentially exclusively to the modules 4 and 5, or B, upstream of which the capacitors 15, 16 are arranged with respect to the supply pins 6, 7, while there is virtually no buffering by the capacitors 15, 16 for the modules 2 and 3 which are arranged upstream of the capacitors 15, 16 with respect to the supply pins 6, 7, i.e. these modules 2, 3 continue to be directly supplied with current without buffering from the supply pins 6, 7 so that their switching currents continue to generate a relatively high level of electromagnetic interference radiation for the environment. These facts can, in other words, also be represented as follows: in the capacitors 15, 16 an electrical charge is stored which can be accessed by the downstream modules 4, 5 in the case of switching currents so that these modules draw current from the capacitors 15, 16 indirectly or in a buffered fashion and not directly from the supply pins 6, 7, from which current charging current flows on into the capacitors 15, 16. However, there is no correspondingly buffered power source available for the modules 2, 4 which directly follow the supply pins 6, 7, for which reason, in the case of switching currents the latter draw charge directly from the supply pins 6, 7, and thus the power source 14. At any rate, the buffers in the form of capacitors 15, 16 for the buffered power supply of the modules 2, 3 are not a possibility, for which reason switching current drawn from these modules directly loads the d.c. source 14 and thus generates interference radiation.
It is accordingly an object of the invention to provide an integrated circuit on a chip, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which has a common power supply of the type mentioned above that is optimized in terms of electromagnetic interference radiation, i.e., it has an EMC-optimized electric power supply.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated circuit formed on a chip, comprising:
a plurality of modules;
common power supply terminals connected to the modules; and
capacitive buffers for buffering the power supply associated with each one of the modules, the capacitive buffers having a capacitance set to cover a dynamic current demand of the modules.
In accordance with an added feature of the invention, power supply tracks extend from the power supply terminals to supply terminals of the modules, and the capacitive buffers are integrated into the power supply tracks.
In accordance with an advantageous feature of the invention, the modules are centrally disposed on the chip, and the power supply tracks extend around the modules in an annular shape.
In accordance with another feature of the invention, the capacitive buffers are formed underneath the power supply tracks.
In other words, the invention provides for complete separation in terms of impedance between the on-chip power supply system and the external power supply. This is achieved in that current is fed via capacitive buffers to each module of the integrated circuit formed on the chip and not only to selected modules as in the case of the prior art explained at the beginning. In other words, each module of the integrated circuit draws its current from a capacitive buffers lying upstream so that the externally supplied current serves exclusively to top up the capacitive buffers with electrical charge. This ensures that electromagnetic interference radiation (EMC, electromagnetic compatibility) is at least considerably reduced in comparison to the prior art because dynamic currents which are drawn on the chip are kept away from the external system and only one more or less uniform recharging current is fed into the power supply system on the chip from the external power supply. In tests it has been possible to determine that interference radiation in the circuit configured according to the invention can be reduced by a factor of 10 in comparison to the system shown in FIGS. 2 and 2A and described in the introductory text above.
The on-chip power supply system according to the invention is advantageously embodied as a ring supply concept with power supply tracks running in an annular shape around the modules arranged at the center of the chip and with capacitive buffers arranged in a neutral fashion in terms of area under these power supply tracks. The capacity of the capacitive buffers is selected in such a way that they are sufficient to at least substantially cover the dynamic power demand of the modules of the integrated circuit.
In accordance with a concomitant feature of the invention, the capacitive buffers are formed as on-chip capacitors.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an EMC-optimized on-chip electric power supply, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.